# listening /dev/cu.usbserial-131210 115200 8N1, start 20:26:00 � [NOTE ] coreboot-26.01rev1 Thu Feb 26 01:49:45 UTC 2026 x86_32 bootblock starting (log level: 7)... [DEBUG] Starting cbfs_boot_device [INFO ] CBFS: Found 'fallback/romstage' @0xf980 size 0x19640 in mcache @0xff7e0e8c [DEBUG] BS: bootblock times (exec / console): total (unknown) / 23 ms [NOTE ] coreboot-26.01rev1 Thu Feb 26 01:49:45 UTC 2026 x86_32 romstage starting (log level: 7)... [DEBUG] Disabling Watchdog reboot... done. [DEBUG] SMBus controller enabled [DEBUG] Setting up static northbridge registers... done. [DEBUG] Started PEG10 link training. [DEBUG] Initializing IGD... [DEBUG] Back from haswell_early_initialization() [DEBUG] CPU id(306c3) ucode:00000028 Intel(R) Core(TM) i3-4150 CPU @ 3.50GHz [DEBUG] AES supported, TXT NOT supported, VT supported [DEBUG] PCH type: Q87, device id: 8c4e, rev id 5 [DEBUG] Starting native platform initialisation [INFO ] Intel ME early init [INFO ] Intel ME firmware is ready [DEBUG] ME: Checking whether CPU was replaced... not replaced [DEBUG] HSIO lane owner: 0x04 [DEBUG] SATA port enables: 0x3f [DEBUG] USB2 port 0 => disabled [DEBUG] USB2 port 1 => disabled [DEBUG] USB2 port 2 => mapped to OC pin 1 [DEBUG] USB2 port 3 => mapped to OC pin 2 [DEBUG] USB2 port 4 => mapped to OC pin 3 [DEBUG] USB2 port 5 => mapped to OC pin 3 [DEBUG] USB2 port 6 => mapped to OC pin 0 [DEBUG] USB2 port 7 => mapped to OC pin 0 [DEBUG] USB2 port 8 => mapped to OC pin 4 [DEBUG] USB2 port 9 => mapped to OC pin 4 [DEBUG] USB2 port 10 => mapped to OC pin 5 [DEBUG] USB2 port 11 => mapped to OC pin 5 [DEBUG] USB2 port 12 => mapped to OC pin 6 [DEBUG] USB2 port 13 => Invalid OC pin 7 for USB2 port 13 [DEBUG] USB3 port 0 => mapped to OC pin 6 [DEBUG] USB3 port 1 => mapped to OC pin 7 [DEBUG] USB3 port 2 => disabled [DEBUG] USB3 port 3 => disabled [DEBUG] USB3 port 4 => mapped to OC pin 1 [DEBUG] USB3 port 5 => mapped to OC pin 2 [DEBUG] Retraining DMI at Gen2 speeds... [DEBUG] DMI: Running at Gen1 x4 [DEBUG] DMI: Running at Gen1 x4 [INFO ] DMI: Running at Gen2 x4 [DEBUG] Programming SA DMI VC/TC mappings... [DEBUG] Programming PCH DMI VC/TC mappings... [DEBUG] Waiting for PCH DMI VC negotiation... done! [DEBUG] Waiting for SA DMI VC negotiation... done! [DEBUG] FMAP: area RW_MRC_CACHE found @ 400000 (65536 bytes) [INFO ] Using cached memory parameters [WARN ] Cannot fast boot: DIMMs have changed [ERROR] raminit failed on step RST_NONT [DEBUG] Found compatible clock / CAS settings [DEBUG] Selected DRAM frequency: 800 MHz [DEBUG] Selected CAS latency : 11T [DEBUG] MPLL busy... done in 7 us [DEBUG] MPLL frequency is set to: 800 MHz (period: 1250000 femtoseconds) [DEBUG] Quadrature clock period: 625 picoseconds [DEBUG] Selected tCK : 1250 ps [DEBUG] Selected tAA : 11T [DEBUG] Selected tWR : 12T [DEBUG] Selected tRCD : 11T [DEBUG] Selected tRRD : 5T [DEBUG] Selected tRP : 11T [DEBUG] Selected tRAS : 28T [DEBUG] Selected tRC : 39T [DEBUG] Selected tRFC : 208T [DEBUG] Selected tWTR : 6T [DEBUG] Selected tRTP : 6T [DEBUG] Selected tFAW : 24T [DEBUG] Selected tCWL : 8T [DEBUG] Selected tCMD : 2T [DEBUG] Selected tREFI : 6240T [DEBUG] Selected tXP : 5T [DEBUG] ME: Requested 0MB UMA [DEBUG] Stage 1: Vref offset training [DEBUG] Hi-Lo (XOR): [DEBUG] C0: 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff [DEBUG] C1: 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff [DEBUG] RdVref: [DEBUG] C0: 1 1 0 0 1 0 1 1 [DEBUG] C1: 1 -1 1 0 1 1 0 1 [DEBUG] Stage 2: Samp offset training [DEBUG] Channel 0 1 [DEBUG] Byte 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 [DEBUG] BitSAmp 77445748 55588755 88977987 9897a9a8 66658745 98968887 77775767 57578556 76656655 ababaa89 85467656 79878979 67697667 66786787 88878878 78867876 [DEBUG] Rank 0 [DEBUG] Steps 1 and 2: Find middle of high region [DEBUG] Update RcvEn timing to be in the center of high region [DEBUG] C0.R0: Left Right Width Center [DEBUG] B0: 248 304 56 276 [DEBUG] B1: 264 320 56 292 [DEBUG] B2: 280 336 56 308 [DEBUG] B3: 304 360 56 332 [DEBUG] B4: 304 368 64 336 [DEBUG] B5: 320 376 56 348 [DEBUG] B6: 328 384 56 356 [DEBUG] B7: 216 280 64 248 [DEBUG] C1.R0: Left Right Width Center [DEBUG] B0: 320 376 56 348 [DEBUG] B1: 336 392 56 364 [DEBUG] B2: 344 400 56 372 [DEBUG] B3: 232 288 56 260 [DEBUG] B4: 248 304 56 276 [DEBUG] B5: 264 320 56 292 [DEBUG] B6: 288 344 56 316 [DEBUG] B7: 304 360 56 332 [DEBUG] Step 3: Quarter preamble - Walk backwards [DEBUG] C0: Preamble [DEBUG] B0: 148 [DEBUG] B1: 164 [DEBUG] B2: 180 [DEBUG] B3: 204 [DEBUG] B4: 208 [DEBUG] B5: 220 [DEBUG] B6: 228 [DEBUG] B7: 248 [DEBUG] C1: Preamble [DEBUG] B0: 220 [DEBUG] B1: 236 [DEBUG] B2: 244 [DEBUG] B3: 260 [DEBUG] B4: 276 [DEBUG] B5: 292 [DEBUG] B6: 316 [DEBUG] B7: 332 [DEBUG] Step 4: Add 1 qclk [DEBUG] Step 5: Walk forward to find rising edge [DEBUG] Step 6: center on preamble and clean up rank [DEBUG] C0: Preamble increment [DEBUG] B0: 189 40 [DEBUG] B1: 203 38 [DEBUG] B2: 216 35 [DEBUG] B3: 239 34 [DEBUG] B4: 243 34 [DEBUG] B5: 253 32 [DEBUG] B6: 270 41 [DEBUG] B7: 287 38 [DEBUG] C1: Preamble increment [DEBUG] B0: 255 34 [DEBUG] B1: 269 32 [DEBUG] B2: 282 37 [DEBUG] B3: 293 32 [DEBUG] B4: 309 32 [DEBUG] B5: 327 34 [DEBUG] B6: 348 31 [DEBUG] B7: 367 34 [DEBUG] Rank 1 [DEBUG] Steps 1 and 2: Find middle of high region [DEBUG] Update RcvEn timing to be in the center of high region [DEBUG] C0.R1: Left Right Width Center [DEBUG] B0: 248 312 64 280 [DEBUG] B1: 264 320 56 292 [DEBUG] B2: 280 336 56 308 [DEBUG] B3: 296 352 56 324 [DEBUG] B4: 304 360 56 332 [DEBUG] B5: 320 376 56 348 [DEBUG] B6: 328 384 56 356 [DEBUG] B7: 344 400 56 372 [DEBUG] Step 3: Quarter preamble - Walk backwards [DEBUG] C0: Preamble [DEBUG] B0: 280 [DEBUG] B1: 292 [DEBUG] B2: 308 [DEBUG] B3: 324 [DEBUG] B4: 332 [DEBUG] B5: 348 [DEBUG] B6: 356 [DEBUG] B7: 372 [DEBUG] Step 4: Add 1 qclk [DEBUG] Step 5: Walk forward to find rising edge [DEBUG] Step 6: center on preamble and clean up rank [DEBUG] C0: Preamble increment [DEBUG] B0: 318 37 [DEBUG] B1: 332 39 [DEBUG] B2: 347 38 [DEBUG] B3: 359 34 [DEBUG] B4: 370 37 [DEBUG] B5: 381 32 [DEBUG] B6: 396 39 [DEBUG] B7: 417 44 [DEBUG] Rank 2 [DEBUG] Steps 1 and 2: Find middle of high region [DEBUG] Update RcvEn timing to be in the center of high region [DEBUG] C0.R2: Left Right Width Center [DEBUG] B0: 264 320 56 292 [DEBUG] B1: 280 336 56 308 [DEBUG] B2: 296 352 56 324 [DEBUG] B3: 304 360 56 332 [DEBUG] B4: 312 368 56 340 [DEBUG] B5: 336 368 32 352 [ERROR] RcvEn: Width of high region (32) too small [ERROR] RcvEn problems on channel 0, byte 5 [ERROR] raminit failed on step RCVET [EMERG] Memory initialization was met with utmost failure and misery